CPU Architecture

Desktop

• x86_64 dominates
• Intel and AMD has duopoly

16-Bit

• x86 instruction set
  • available in 16 bit, 32 bit (IA32) or 64 bit (x86_64) also
  • 8086, 8088 (Intel)

32 Bit

• IA32 instruction set
  • In modern context it is also referred as x86
  • Intel Pentium

64 Bit

• x86_64 instruction set — developed by AMD
  • aka AMD64
  • sold by Intel and AMD
  • Intel Core 2 Duo
  • AMD Ryzen 5 4600H
• AArch64 instruction set — introduced in ARMv8-A
  • aka ARM64
  • sold by Apple
  • Apple M1/M2

Mobile

• AArch64 dominates
• ARM designs but do not manufacture

32 Bit

• AArch32 instruction set — till ARMv7-A
  • aka ARM32
  • sold by Snapdragon, Samsung, Apple
  • Apple A6

64 Bit

• AArch64 instruction set — introduced in ARMv8-A
  • aka ARM64
  • sold by Snapdragon, Samsung, Apple
  • Apple A7
  • Apple A12 Bionic
  • Samsung Exynos 850
  • Snapdragon 710

ISA

• Base ISA handle fundamental computing math and logic
• Extensions add more capabilities

ISA Types

• RISC (Reduced Instruction Set Computer)
  • Highly simplified set of instructions optimized to execute in a single clock cycle
  • It prioritizes power efficiency and smaller chip sizes
  • Examples
    • AArch64 (ARM64)
    • RISC-V
    • MIPS
• CISC (Complex Instruction Set Computer)
  • Complex instruction set where a single command can perform multiple operations
    • Example: loading from memory, adding numbers, and storing back to memory
  • It prioritizes reducing the overall number of lines of code
  • Examples
    • x86_64
• VLIW (Very Long Instruction Word)
  • Shifts the burden of managing parallel instruction execution away from hardware timers and onto the software compiler
  • Examples
    • IA-64 (Intel Itanium)

ISA Extensions

• SIMD and Vector extensions
  • x86:
    • AVX2 (Advanced Vector Extensions 2)
    • AVX-512 (512-bit AVX)
    • AVX10 (AVX 10)
  • ARM
    • NEON (Advanced SIMD)
    • SVE2 (Scalable Vector Extensions 2)
• Matrix and AI Accelerator
  • Intel AMX (Advanced Matrix Extensions)
  • ARM SME (Scalable Matrix Extensions)
• Cryptography and Security
  • AES-NI (AES New Instructions)
  • Intel SGX (Software Guard Extension)
  • AMD SEV (Secure Encrypted Virtualization)

Example ISA

• https://instructionsets.com/
• Intel x64
  • https://www.intel.com/content/www/us/en/content-details/782158/intel-64-and-ia-32-architectures-software-developer-s-manual-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4.html
• AMD64
  • https://www.scs.stanford.edu/~zyedidia/docs/x86/amd-manual.pdf
• ARM v8 (ARM64)
  • ???
• RISC-V
  • https://docs.riscv.org/reference/home/index.html

Parallelism in Computer Architecture

• Data Level Parallelism (DLP)
  • SIMD (Single Instruction, Multiple Data) / Vector processing
• Instruction Level Parallelism (ILP)
  • Superscalar
  • Out of order execution (OoO)
  • VLIW (Very Long Instruction Word)
• Thread Level Parallelism (TLP)
  • Multithreading
  • SMT (Simultaneous Multithreading)
  • SIMT (Single Instruction, Multiple Threads)
  • MIMD (Multiple Instruction, Multiple Data) / Multicore