CPU

• Central Processing Unit
• Dataset: https://www.techpowerup.com/cpu-specs
• Example: https://www.techpowerup.com/cpu-specs/ryzen-5-4600h.c2283

CPU Components

• CPU Core
  • Instruction Processing
    • Instruction Fetch Unit
    • Instruction Decode Unit
    • Branch Prediction Unit
  • Control Unit (CU)
  • Execution Units
    • Arithmetic and Logic Unit (ALU)
    • Floating Point Unit (FPU)
    • SIMD/Vector Unit
  • Registers
  • Load/Store Unit
  • L1/L2 Cache
  • Memory Management Unit (MMU)
  • Clock and Timing Unit
• Shared L3 Cache
• Internal Interconnect
• Integrated Memory Controller (IMC)
• PCIe Root Complex

CPU Integrated Controllers and Interfaces

• Integrated Memory Controller (IMC)
• PCIe Controller / Root Complex
• Interconnect / Fabric (architecture-dependent)

flowchart TD
    subgraph CPU["CPU"]
        subgraph CORE0["Core 0"]
            direction TB
            L1_0["L1 Cache"]
            L2_0["L2 Cache"]
            L1_0 --> L2_0
        end

        subgraph CORE1["Core 1"]
            direction TB
            L1_1["L1 Cache"]
            L2_1["L2 Cache"]
            L1_1 --> L2_1
        end

        CORE0 <--> FAB["Internal Interconnect"]
        CORE1 <--> FAB

        FAB <--> L3["Shared L3 Cache"]
        FAB <--> IMC["Integrated Memory Controller"]
        FAB <--> RC["PCIe Root Complex"]
    end

    DDR["DDR Memory Bus"]
    RAM["Main Memory (RAM)"]

    IMC <--> DDR
    DDR <--> RAM

Thermal Paste

• Fills microscopic gaps between top of CPU and contact plate of CPU cooler
• Since air is poor conductor, thermal paste helps to conduct the heat

CPU Cooler

• Connected via CPU Cooler header
• Components
  • Heatsink
  • Fans
  • Contact Plate

CPU Features

Clock

• Clock Frequency
  • How many clock cycles CPU perform per second
  • It represents the rate of the CPU clock
  • Example: 3 GHz
• Base Clock Frequency (BCLK)
  • Reference clock used by CPU operating frequencies
  • Example: 100 MHz (Typical for modern PCs)
• CPU Multiplier
  • A multiplication factor applied to BCLK to get core frequency
  • Example: 30x (30x100MHz = 3 GHz)
• Turbo/Boost Clock Frequency
  • Higher frequency that the CPU can reach when conditions allow it
  • Example: up to 4 GHz

Architecture

• Processor size
  • Approx transistor size
  • Example: 7nm
• Memory Support
  • Example: DDR4
• Memory Bus
  • Example: Dual-Channel
• Memory Bandwidth
  • Example: 51 GB/s
• PCI-Express
  • Example: Gen 3

Core Config

• Number of Cores
  • Physical CPU Cores
  • Example: 6
• Number of Logical Cores
  • aka Hardware Threads or Logical Processors
  • Number of hardware execution contexts supported by the CPU
  • SMT (Simultaneous Multithreading) allow one physical core to support multiple hardware threads
  • Example: 12 (2 Hardware thread per core for 6 cores)

Cache

• Implemented using SRAM
• L1 Cache
  • Smallest and fastest CPU cache
  • Often split into
    • L1 Instruction Cache (L1i)
    • L1 Data Cache (L1d)
  • Example: 64 KB (32 KB L1i + 32KB L1d) per core
• L2 Cache
  • Larger but slower than L1
  • Example: 512 KB per core
• L3 Cache
  • Larger and slower than L2
  • Example: 8 MB shared

flowchart TD
    CPU["CPU"]

    CPU --> C0["Core 0"]
    CPU --> C1["Core 1"]

    C0 --> L1_0["L1 Cache"]
    L1_0 --> L2_0["L2 Cache"]

    C1 --> L1_1["L1 Cache"]
    L1_1 --> L2_1["L2 Cache"]

    L2_0 --> L3["L3 Cache"]
    L2_1 --> L3

    L3 --> RAM["Main Memory - RAM"]

Features

• Base ISA
  • AMD64
• ISA Extensions
  • SIMD
    • MMX
    • SSE, SSE2, SSE3
    • SSSE3, SSE4A, SSE4.1, SSE4.2
    • AVX, AVX2
  • Cryptographic
    • AES
    • SHA
  • Bit Manipulation
    • BMI1
    • BMI2
  • Floating-Point
    • F16C
    • FMA3
• Virtualization
  • AMD-V
• Security Protection
  • SMAP (Supervisor Mode Access Prevention)
    • Prevents OS kernel from accidentally accessing user-space memory
  • SMEP (Supervisor Mode Execution Prevention)
    • Prevents OS kernel from executing code located in user-space memory
• Execution/Performance Technology
  • SMT (Simultaneous Multithreading)
    • allows one physical core to maintain multiple hardware threads
  • Superscalar
    • allows CPU to execute multiple instructions per clock cycle
  • Out of Order
    • allows CPU to execute ready instructions before earlier instructions that are waiting on dependencies or resources
• Power / Performance Management
  • Precision Boost 2
    • dynamically adjusts CPU frequency based on operating conditions

CPU Performance Equations

• Execution time is the only valid and unimpeachable measure of performance
• Clock Rate
  • How many clock cycles in 1 second

$$\text{Clock Rate}=\frac{\text{Clock Cycles}}{\text{Second}}$$

• Clock Cycle Time
  • How many seconds in 1 clock cycle

$$\text{Clock Cycle Time}=\frac{\text{Seconds}}{\text{Clock Cycle}}=\frac{1}{\text{Clock Rate}}$$

• Clock Cycles per Instruction (CPI) of a program
  • Avg number of clock cycles each instruction takes to execute in a program

$$\text{CPI}=\frac{\text{Total clock cycles}}{\text{Total number of Instructions}}$$

• Relationship

$$\frac{\text{Seconds}}{\text{Program}}=\frac{\text{Instructions}}{\text{Program}}\cdot \frac{\text{Clock Cycles}}{\text{Instructions}}\cdot \frac{\text{Seconds}}{\text{Clock Cycle}}$$

• Classic CPU Performance Equation

$$\text{CPU Time}=\text{Instruction count}\cdot \text{CPI}\cdot \text{Clock cycle time}=\frac{\text{Instruction count}\cdot \text{CPI}}{\text{Clock Rate}}$$

• CPU time in MIPS (Million Instructions per second)
  • Instruction execution rate

$$\text{MIPS}=\frac{\text{Instruction count}}{\text{CPU Time}\cdot 10^6}$$

• Pitfalls and Fallacies
  • Pitfall: Expecting the improvement of one aspect of a computer to increase overall performance by an amount proportional to the size of the improvement
  • Fallacy: Computers at low utilization use little power
  • Pitfall: Using a subset of the performance equation as a performance metric